1. Field of the Invention
The invention relates to a data processing device for the processing of data words which are composed of k=2p-2.gtoreq.2 data symbols by means of code words which are formed from the associated data words by means of an error-correcting code, said code words containing n=2p code symbols, all symbols consisting of m=2s.gtoreq.4 bits and forming part of a Galois field GF (2.sup.m)={0, a.sup.0, a.sup.1 . . . a.sup.2.spsp.m.sup.-2 }, said device comprising a first input for a data word, first multiplier means for multiplying the data word by a generator matrix [G] consisting of nxk matrix elements each of m bits in order to form a code word, processing means for processing the code word in order to form a processing result, and reconstruction means for reconstructing, using a parity check matrix [R] which is orthogonal to the generator matrix [G], the second data word associated with the processing result for output on a first output.
2. Description of the Prior Art
A device of this kind is known from U.S. Pat. No. 4,402,045 in the name of Applicant. The known device specifically concerns a multiprocessor computer system in which the digital data processing is organized according to n parallel processors for each processing the data word and in which the data storage is organized according to n memories which each store one respective code symbol of a resulting code word. The known device implements an error-correcting code which can operate in two modes:
(a) in a first, symbol-correcting operating mode one arbitrarily disturbed symbol can be corrected;
(b) in a second mode, referred to as the erasure mode, by ignoring a given symbol, for example a suspect symbol, a one-bit error in addition to the ignored symbol can be corrected.